1. Technical Field
The invention relates generally to semiconductor devices, and more specifically, to packaging in semiconductor devices.
2. Background Art
In a conventional semiconductor integrated-circuit package, electrical connections to the bonding pads of a chip may be provided through a thin metal leadframe, which is typically stamped or chemically etched from strips of copper-containing materials. The leadframe includes a number of thin, closely-spaced conductive inner leads that radially extend away from the edges of the chip. The inner leads diverge away from the chip and extend through the exterior walls of the molded package where they form the external I/O leads for the package.
Some examples of conventional semiconductor integrated-circuit packages are found in the following U.S. Patents: U.S. Pat. No. 3,978,516, "Lead Frame Assembly for a Packaged Semiconductor Microcircuit" issued August 1976 to Noe; U.S. Pat. No. Re. 35,353, "Process for Manufacturing a Multi-Level Lead Frame" issued October 1996 to Tokita et al.; and U.S. Pat. No. 5,365,409, "Integrated Circuit Package Design Having an Intermediate Die-Attach Substrate Bonded to a Leadfranie" issued November 1994 to Kwon et al. In the aforementioned patents, thin-film and thick-film material is used to form unique inner leads to increase speed and/or flexibility of conventional semiconductor packages.
One problem, though, with conventional semiconductor packages is that the current lead lengths are too inductive for the increased speed of operations of DRAMs. As chip sizes are reduced, the length of the lead frame segment to package edge increases, further increasing inductance. This excessive lead inductance results in degraded electrical performance of the package. Furthermore, the chip I/O pitch is limited because of the leadframe fabrication capabilities and package stresses are created when large chips are mechanically coupled to the leadframe inside a plastic encapsulated package.